Home > Advanced Projects > Frequency Meter/Counter > Circuit Description

Modified: 15:09, 27 October 2013


frequency meter block diagram


The heart of the system is the Control Logic. This provides the correct connection of signals to perform the units functions, such as latching, gate timing and control, enabling and resetting of counters, control of clock inputs and speeds. The timebase is generated from By combining timings and controls of the counters, various functions can be achieved. These are detailed later on.

The IC's are 74HC type offering high speed with low current consumption. Since the circuit is quite complex, I will divide it into sections.

Complete Circuit Diagram - updated

Seems a good place to start. The timebase runs from a 10MHz crystal oscillator fed to a series of decade counters. Taps from these are taken at 10MHz, 1MHz, 1KHz, 10Hz and 1Hz. The crystal oscillator is formed from 2 Schmitt NOT gates (74HC14) and then to 7 decade counters, the CarryOut from each driving the clock of the next. Since the CarryOuts have an even mark/space ratio, they can provide synchronised signals at lower frequencies. These are used to drive the Counter Array and some of the Control Logic. Note the decoupling capacitors next to each chip - chuffed with good design!
crystal oscillator time base array

Crystal oscillator (IC6) on left connected to the 7 decade counters in a row .

This section comprises of 8, 4bit BCD ripple counters in series (IC14-17), the last 5 stages are connected to the Display Decoder. The clocks are fed from the previous digit MSB (most significant bit) and the counters advance on the low-going edge of the pulse.

There are 4 clock inputs to the counters fed to stages 0,1,3 and 4. These are ANDed with previous stage outputs (active low signals need AND gates to OR them together) to allow either to access the clocks. In Frequency Counter mode, these inputs allow the following functions:

1KHz - 99,999KHz
1KHz - 99,999KHz
1Hz - 99,999Hz
10Hz - 99,990Hz

In Counter and Timer modes, Clk3 is used to access the first displayed digit directly without any prescaling.

The Carry Out from the final stage feeds 2 D-type flip/flops. The first will latch any overflow, and the second displays it when the LE for the display goes high. The NOT gates are needed since the clock uses a positive edge and the reset is active low.

counter array

Least significant counter on the left, (IC14-17), then NOT gates (IC25) and D-type F/F (IC18). AND gates (IC24) horizontal IC below counters.
And...more de-coupling capacitors!

The display decoder comprises of 5 BCD-7segment decoders (IC19-23) which can produce up to 25mA per output, but they do get a bit warm...to say the least. The resistors in series with each segment are 100 ohms. The voltage drop of the displays is about 2.2 volts being green not red so the current to each segment will be

V/R = I so (5-2.2)/100 = 0.028A or 28mA

OK a bit on the high side but these are old displays and need a good kicking! More modern displays will only need about 20mA so use 150ohm upwards, higher if using hi-brightness red ones.

All LE (latch enables) are connected together and used to latch in the value from the counters after each sample count has completed, allowing the counters to reset and begin the next sample count. This maintains a steady display that only changes every 0.1 or 1 second (depending on GATE time)

display decoders
A view of the 5 decoder/drivers with the series resistors to the LED displays.
And guess what? More decoupling capacitors!
This is the main control section. It provides control over the signals to varoius parts of the counter to ensure correct readings. The principle is very simple when broken down into the 3 functions.

The principle of frequency measurement is simple. Since frequency is a measure of pulses per second, simply reset the counter and count the number of input pulses in 1 second, then display it.

This sequence is controlled by IC1-4. IC1a is a D-type F/F that is clocked by 1Hz/10Hz (SW5) from the timebase. This is the gate time. IC2 is a decade counter with separate outputs, 4 of which are used. Its clock is 1MHz from the timebase as the latch/reset sequence needs to be over as quickly as possible for accurate readings.

Assuming the Q output of the F/F is low, then NotQ is high holding IC2 in reset. When the F/F is clocked the sequence begins as follows:

NotQ of the F/F goes low, allowing the sequencer to count. On each clock pulse the following occurs
  • Output 1 goes high sending LE low via the NOR gate IC3. This enables the counter BCD values into the display decoder IC's - display updates
  • Output 1 goes low, 2 goes high, values are latched into decoders
  • Output 2 goes low, 3 goes high, sending RCTR high via gates IC3. This resets the counters.
  • Output 3 goes low, 4 goes high, releasing the counters from reset allowing them to start counting the next sample.
  • Output 4 goes low, 5 goes high disabling the sequencer/counter and resetting the F/F. This in turn sends NotQ high resetting the sequencer.

This happens in 6 x 1us clock pulses = 6us. This is fast enough not to affect any frequencies up to about 100KHz. Frequencies above that will be shown in KHz anyway so to the nearest thousand and any lost input pulses will not show up on the display.

On the next gate pulse the process is repeated. The clock to the counters is routed via SW1,4,5. By selecting various stages of the counter array, the 2 ranges Hz/KHz and 2 gate speeds 1/10Hz can be selected. It is simple to work out if you study the diagram and far too long winded to explain. Sorry. SW3/4 select the correct LED's to illuminate indicating range and gate time.

Using multipole switches is a crude but effective way of achieving these results. With more time it may be prudent to use analogue switches for dust free operation but it has worked well for the past 6 years so I doubt weather it will happen.


Explanation pending


Explanation pending - really tired!!



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